Buried conductor for imagers

ABSTRACT

A pixel cell having a photo-conversion device at a surface of a substrate and at least one contact area from which charge or a signal is output or received. A first insulating layer is located over the photo-conversion device and the at least one contact area. The pixel cell further includes at least one conductor in contact with the at least one contact area. The conductor includes a polysilicon material extending through the first insulating layer and in contact with the at least one contact area. Further, a conductive material, which includes at least one of a silicide and a refractory metal, can be over and in contact with the polysilicon material.

FIELD OF THE INVENTION

The present invention relates generally to the field of semiconductordevices and more particularly to improved conductors for use in imagesensors.

BACKGROUND OF THE INVENTION

CMOS image sensors are increasingly being used as a low cost alternativeto charge coupled device (CCD) image sensors. In a CMOS image sensor,the active elements of a pixel cell perform the necessary functions of:(1) photon to charge conversion; (2) accumulation of image charge; (3)transfer of charge to the sensing node accompanied by chargeamplification; (4) resetting the sensing node to a known state beforethe transfer of charge to it; (5) selection of a pixel for readout; and(6) output and amplification of a signal representing pixel charge fromthe sensing node.

CMOS image sensors of the type discussed above are generally known asdiscussed, for example, in Nixon et al., “256×256 CMOS Active PixelSensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol.31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active PixelImage Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp.452-453 (1994). Exemplary CMOS image sensor circuits, processing stepsthereof, and detailed descriptions of the functions of various CMOSelements of an image sensor circuit are described, for example, in U.S.Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524, and6,333,205, assigned to Micron Technology, Inc. The disclosures of eachof the forgoing patents are herein incorporated by reference in theirentirety.

FIG. 1A is schematic diagram of a conventional CMOS pixel cell 1, whichincludes conventional pixel cells 10. FIG. 1B shows a top plan view of apixel cell 10 of FIG. 1A, while FIG. 1C shows a cross-sectional view ofthe pixel cell 10 of FIG. 1B along line 1C-1C′. Typically, the pixelcells 10 are formed at a surface of a substrate 11 (FIG. 1C). A pixelcell 10 is isolated from other pixel cells 10 and peripheral circuitry(not shown) by an isolation region 12 (FIG. 1C), which is shown as ashallow trench isolation (STI) region. The substrate 11 is doped to afirst conductivity type, e.g., p-type and is biased at a groundpotential.

As is known in the art, a pixel cell 10 functions by receiving photonsof light and converting those photons into charge carried by electrons.For this, each one of the pixel cells 10 includes a photo-conversiondevice 21, which is shown as a pinned photodiode, but can be anon-pinned photodiode, photogate, photoconductor, or otherphotosensitive device. The photodiode 21 includes an n-type photodiodecharge accumulation region 22 and a p-type surface layer 23 (FIG. 1C).

Each pixel cell 10 also includes a transfer transistor 27, whichreceives a transfer control signal TX at its gate electrode 30 b. Thetransfer transistor 27 is connected to the photodiode 21 and a floatingdiffusion region 25. During operation, the TX signal operates thetransfer transistor 27 to transfer charge from the photodiode chargeaccumulation region 22 to the floating diffusion region 25.

The pixel cell 20 further includes a reset transistor 28, which receivesa reset control signal RST at its gate electrode 30 b. The resettransistor 28 is connected to the floating diffusion region 25 andincludes a source/drain region 60 coupled to a voltage supply, Vaa-pix,through a contact 61. In response to the RST signal, the resettransistor 28 operates to reset the diffusion region 25 to apredetermined charge level Vaa-pix.

A source follower transistor 29 has a gate electrode 30 b coupled to thefloating diffusion region 25 through a contact 61 that receives andamplifies a charge level from the diffusion region 25. The sourcefollower transistor 29 also includes a first source/drain region 60coupled to the power supply voltage, Vaa-pix, and a second source/drainregion 60 connected to a row select transistor 26. The row selecttransistor 26 receives a row select control signal ROW_SEL at its gateelectrode 30 b. In response to the ROW_SEL signal, the row selecttransistor 26 couples the pixel cell 10 to a column line 22, which iscoupled to a source/drain region 60 of the row select transistor 26.When the row select gate electrode 30 b is operated, an output voltageis output from the pixel cell 20 through the column line 22.

As shown in FIG. 1C, the transistor gates 30 b are part of gate stacks30. Although, FIG. 1C shows only the transfer transistor 27 and resettransistor 28 having gate stacks 30, the source follower transistor 29and the row select transistor 26 also include respective gate stacks 30.The gate stacks 30 generally include a first insulating layer 30 a,which serves as the gate oxide layer. A layer of conductive material 30b, which serves as the gate electrode, is deposited over the firstinsulating layer 30 a. A gate stack insulating layer 30 c is depositedover the gate electrode 30 b. Additionally, the gate stacks 30 caninclude layers of high conductivity material between the gate electrode30 b and the gate stack insulating layer 30 c, such as a silicide layeror a barrier layer and a refractory metal layer. Dark current, however,can increase dramatically when such highly conductive materials areincluded in the gate stacks 30 of a pixel cell 10.

It is desirable to have a pixel cell including low resistance conductorsthat would not result in increased dark current.

BRIEF SUMMARY OF THE INVENTION

Exemplary embodiments of the invention provide a pixel cell having aphoto-conversion device at a surface of a substrate and at least onecontact area from which charge or a signal is output or received. Afirst insulating layer is located over the photo-conversion device andthe at least one contact area. The pixel cell further includes at leastone conductor in contact with the at least one contact area. Theconductor includes a polysilicon material extending through the firstinsulating layer and in contact with the at least one contact area.Also, a conductive material, which includes at least one of a silicideand a refractory metal, can be and in contact with the polysiliconmaterial.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages and features of the invention willbecome more apparent from the detailed description of exemplaryembodiments provided below with reference to the accompanying drawingsin which:

FIG. 1A is a schematic diagram of conventional CMOS pixel cells;

FIG. 1B is a top plan view of a pixel cell of FIG. 1A;

FIG. 1C is a cross-sectional view of the pixel cell of FIG. 1B takenalong the line 1C-1C′;

FIG. 2 is a cross-sectional view of a pixel cell according to anexemplary embodiment of the invention;

FIGS. 3A-3I depict the pixel cell of FIG. 2 at various stages ofprocessing;

FIG. 4 is a cross-sectional view of a pixel cell according to anotherexemplary embodiment of the invention;

FIG. 5 is a cross-sectional view of a pixel cell according to anotherexemplary embodiment of the invention;

FIG. 6 is a block diagram of a CMOS image sensor according to anexemplary embodiment of the invention; and

FIG. 7 is a block diagram of a processor system including the CMOS imagesensor of FIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof and illustrate specificembodiments in which the invention may be practiced. In the drawings,like reference numerals describe substantially similar componentsthroughout the several views. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized, and that structural, logical and electrical changes may bemade without departing from the spirit and scope of the presentinvention.

The terms “wafer” and “substrate” are to be understood as includingsilicon, silicon-on-insulator (SOI), or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. In addition, the semiconductorneed not be silicon-based, but could be based on silicon-germanium,germanium, or gallium-arsenide.

The term “pixel” or “pixel cell” refers to a picture element unit cellcontaining a photo-conversion device for converting electromagneticradiation to an electrical signal.

Referring to the drawings, FIG. 2 depicts a cross-sectional view of apixel cell 200 according to an exemplary embodiment of the invention.The pixel cell 200 is similar to the pixel cell 10 depicted in FIGS.1A-1C, except that the pixel cell 200 includes low resistance (i.e.,high conductivity) conductors 270. Also, the pixel cell 200 may includea p-type well 241 surrounding and below the isolation region 12 and ap-type well 242 below the floating diffusion region 25, the resettransistor 28, and a portion of the transfer transistor 27. Further, asshown in FIG. 2, first, second, third, and fourth insulating layers 233,234, 250, 251, respectively, are formed over the substrate 11 and thegate stacks 30. Portions of the first insulating layer 233 form sidewallspacers on the gate stacks 30.

The conductors 270 are in contact with conductive areas 277 from whichcharge or a signal can be output and/or received. Thus, conductors 270can serve to route various lines 70 (e.g., row lines, output signallines, power supply lines, and/or periphery circuitry) to the pixel cell200. FIG. 2 depicts conductors 270 in contact with the gate electrodes30 b of the transfer transistor 27 and the reset transistor 28, thefloating diffusion region 25, and a source/drain region 60 of the resettransistor 28. The conductors 270 include first and second conductivelayers 271, 272, respectively. The first and second conductive layers271, 272 are formed through the second and third insulating layers 234,250. For the conductors 270 in contact with a gate electrode 30 b, thefirst conductive layer 271 also extends through the gate stackinsulating layer 30 c.

Preferably, the first conductive layer 271 is a layer of polysilicon.The second conductive layer 272 is formed over the first conductivelayer 271. The second conductive layer 272 can be a layer of a singlematerial or a composite layer comprising layers of more than onematerial. For example, the second conductive layer 272 can be a silicidelayer, such as tungsten silicide, titanium silicide, tungsten silicide,cobalt silicide, molybdenum silicide, or tantalum silicide, amongothers; or a barrier metal/refractory metal layer, such as tungstennitride (WN_(x))/tungsten, titanium nitride/tungsten (TiN/W), amongothers.

As described in more detail below, the conductors 270 are formed afterthe photodiode 21 and the first several insulating layers 233, 234, and250 are formed. Therefore, the photodiode 21 is protected by theinsulating layers 233, 234, and 250 when the conductors 270 are formed.In this manner, dark current is not increased by the formation of theconductors 270.

FIGS. 3A-3I depict the formation of pixel cell 200 according to anexemplary embodiment of the invention. No particular order is requiredfor any of the actions described herein, except for those logicallyrequiring the results of prior actions. Accordingly, while the actionsbelow are described as being performed in a general order, the order isexemplary only and can be altered if desired.

FIG. 3A illustrates a pixel cell 200 at an initial stage of fabrication.In the illustrated exemplary embodiment, the substrate 11 is a siliconsubstrate of a first conductivity type, which, for this exemplaryembodiment is p-type. An isolation region 12 is formed in the substrate11 and filled with an insulating material. The insulating material maybe an oxide material, for example a silicon oxide; oxynitride; a nitridematerial, such as silicon nitride; silicon carbide; a high temperaturepolymer; or other suitable insulating material. As shown in FIG. 3A, theisolation region 12 can be a shallow trench isolation (STI) region. Theinsulating material for the STI region 12 is preferably a high densityplasma (HDP) oxide, a material which has a high ability to effectivelyfill narrow trenches.

Doped p-type wells 241, 242 are implanted into the substrate 11 as alsoshown in FIG. 3A. The p-wells 241, 242 are formed in the substrate awayfrom the area where the photodiode 21 (FIG. 2) is to be formed. Thep-wells 241, 242 can be shared with an adjacent pixel cell (not shown).The p-wells 241, 242 are formed by any known method. For example, alayer of photoresist (not shown) can be patterned over the substrate 11having an opening over the area where the p-wells 241, 242 are to beformed. A p-type dopant, such as boron, can be implanted into thesubstrate 11 through the opening in the photoresist. The p-wells 241,242 are formed having a p-type dopant concentration that is higher thanadjacent portions of the substrate 11.

FIG. 3B depicts the formation of the transfer transistor 27 (FIG. 2) andthe reset transistor 28 (FIG. 2) gate stacks 30. Although not shown, thesource follower and row select transistors 29, 26 (FIGS. 1A and 1B),respectively, can be formed concurrently with the transfer and resettransistors 27, 28, as described below.

To form the gate stacks 30, a first insulating layer 30 a of, forexample, silicon oxide is grown or deposited on the substrate 11. Thefirst insulating layer 30 a serves as the gate oxide layer for thesubsequently formed transistor gate electrode 30 b. Next, a layer ofconductive material 30 b is deposited over the oxide layer 30 a. Theconductive layer 30 b serves as the gate electrode for the transistors27, 28 (FIG. 2). The gate electrode 30 b may be a layer of polysilicon,which may be doped to a second conductivity type, e.g., n-type. A secondinsulating layer 30 c, referred to herein as the gate stack insulatinglayer, is deposited over the gate electrode 30 b. The gate stackinsulating layer 30 c may be formed of, for example, TEOS, a siliconoxide (SiO₂), a nitride (e.g., silicon nitride), an oxynitride (siliconoxynitride), ON (oxide-nitride), NO (nitride-oxide), or ONO(oxide-nitride-oxide).

The gate stack layers 30 a, 30 b, 30 c may be formed by conventionalmethods, such as grown in a furnace, chemical vapor deposition (CVD) orplasma enhanced chemical vapor deposition (PECVD), among others. Thelayers 30 a, 30 b, 30 c are then patterned and etched to form themultilayer gate stacks 30 shown in FIG. 3B.

The invention is not limited to the structure of the gate stacks 30described above. Additional layers may be added or the gate stacks 30may be altered as is desired and known in the art.

As depicted in FIG. 3C, a doped n-type region 22 is implanted in thesubstrate 11. For example, a layer of photoresist (not shown) may bepatterned over the substrate 11 having an opening over the surface ofthe substrate 11 where photodiode 21 (FIG. 2) is to be formed. An n-typedopant, such as phosphorus, arsenic, or antimony, may be implantedthrough the opening and into the substrate 11. Multiple implants may beused to tailor the doping profile of region 22. If desired, an angledimplantation may be conducted to form the doped region 22, such thatimplantation is carried out at angles other than 90 degrees relative tothe surface of the substrate 11.

As shown in FIG. 3C, the n-type region 22 is formed from a pointadjacent the transfer gate stack 30 and extending within the substrate11 between the transfer gate stack 30 and the isolation region 12. Theregion 22 forms a photosensitive charge accumulating region forcollecting photo-generated charge.

The floating diffusion region 25 and source/drain region 60 areimplanted by known methods to achieve the structure shown in FIG. 3C.The floating diffusion region 25 and source/drain region 60 are formedas n-type regions. Any suitable n-type dopant, such as phosphorus,arsenic, or antimony, may be used. The floating diffusion region 25 isformed on the side of the transfer gate stack 30 opposite the n-typephotodiode region 22. The source/drain region 60 is formed on a side ofthe reset gate stack 30 opposite the floating diffusion region 25.

FIG. 3D depicts the formation of a first insulating layer 233. Thislayer 233 can be any appropriate insulating material, such as tetraethylorthosilicate (TEOS), silicon dioxide, silicon nitride, an oxynitride,among others, formed by methods known in the art.

FIG. 3E illustrates the formation of the surface layer 23 within thesubstrate 11. In the illustrated embodiment, a p-type dopant, such asboron, indium, or any other suitable p-type dopant, may be used to formthe p-type surface layer 23. Alternatively, if desired, the surfacelayer 23 can be formed before the n-type region 22 (FIG. 3C).

The first insulating layer 233 is etched as shown in FIG. 3E. Theremaining portions of layer 233 form sidewall spacers on the sidewall ofthe reset gate stack 30 and a sidewall of the transfer gate stack 30.Layer 233 remains over a portion of the transfer gate stack 30 and thephotodiode 21. Alternatively, the first insulating layer 233 can bepatterned/etched such that only sidewall spacers (not shown) remain onthe gate stacks 30.

Optionally, a second insulating layer 234 (e.g., a TEOS layer) can beformed over the first insulating layer 233 to achieve the structureshown in FIG. 3E.

As depicted in FIG. 3F, a third insulating layer 250 is formed over thesecond insulating layer 234. In the embodiment of FIG. 3F, the thirdinsulating layer 250 is a layer of borophosphosilicate glass (BPSG).Instead, the third insulating layer could be, for example, silicondioxide, borosilicate glass (BSG), or phosphosilicate glass (PSG), amongothers. The third insulating layer 250 is planarized by, for example, achemical mechanical polish (CMP) step.

As shown in FIG. 3G, openings 252, 253 are formed in the secondinsulating layer 234 and the third insulating layer 250. The openings252, 253 can be formed by any known technique. The openings 252 areformed to expose the gate electrodes 30 b of the gate stacks 30. Theopenings 253 are formed to expose the floating diffusion region 25 andsource/drain region 60.

FIG. 3H depicts the formation of a first conductive layer 271 that fillsthe openings 252, 253. Preferably, the first conductive layer 271 is alayer of polysilicon. A second conductive layer 272 is formed over thefirst conductive layer 271. The second conductive layer 272 can be alayer of a single material or a composite layer comprising layers ofmore than one material. For example, the second conductive layer 272 canbe a silicide layer, such as tungsten silicide, titanium silicide,cobalt silicide, molybdenum silicide, or tantalum silicide, amongothers; or a barrier metal/refractory metal layer, such as tungstennitride (WN_(x))/tungsten, titanium nitride/tungsten (TiN/W), amongothers. It should be noted that the second conductive layer 272 is notrequired for applications where low resistance is not needed.

The first and second conductive layers 271, 272 are patterned to formthe conductors 270, as shown in FIG. 3I. As noted above, dark current isnot significantly increased by the formation of the conductors 270,since the photodiode 21 is protected when the conductors 270 are formed.In the illustrated embodiment, the photodiode 21 is protected by thefirst, second, and third insulating layers 233, 234, 250.

A fourth insulating layer 251 is formed over the conductors 270 andthird insulating layer 250 to achieve the structure shown in FIG. 2. Thefourth insulating layer 251 can be, for example, silicon dioxide, BSG,PSG, or BPSG. Conventional processing methods are used to form otherstructures (not shown) of the pixel 200. For example, shielding, andmetallization layers to connect conductors 270 to row lines 70; andother connections of the pixel 200 are formed.

FIG. 4 is a cross-sectional view of a pixel cell 400 according toanother exemplary embodiment of the invention. The pixel cell 400 issimilar to pixel cell 200 (FIG. 2), except that the first conductivelayer 271 is formed only within the third insulating layer 250. Thepixel cell 400 can be formed as described above in connection with FIGS.3A-3I, except that after the first conductive layer 271 is formed andbefore the second conductive layer is formed, the first conductive layer271 is planarized by, for example, a chemical mechanical polish (CMP)step. Accordingly, only the second conductive layer 272 is patterned.

Additionally, in the FIG. 4 embodiment, the second conductive layer 272can further include a polysilicon layer. Thus, the second conductivelayer 272 can, for example, have a polysilicon/silicide or apolysilicon/barrier metal/refractory metal layering structure.

FIG. 5 is a cross-sectional view of a pixel cell 500 according toanother exemplary embodiment of the invention. The pixel cell 500 issimilar to the pixel cell 200 (FIG. 2), except that the third planarizedinsulating layer 250 is omitted. The pixel cell 500 can be formed asdescribed above in connection with FIGS. 3A-3I, except that the step offorming the third planarized insulating layer 250 is omitted and theopenings 252 are formed through the second insulating layer 234 and thegate insulating layer 30 c; and the openings 253 are formed through thesecond insulating layer 234.

Although the above embodiments are described in connection with 4T pixelcell 200 (FIG. 2), 400 (FIG. 4), and 500 (FIG. 5), the configuration ofthe pixel cells 200, 400, 500 is only exemplary and the invention mayalso be incorporated into other pixel circuits having different numbersof transistors. Without being limiting, such a circuit may include athree-transistor (3T) pixel cell or a five (5T) or more transistor pixelcell. A 3T cell omits the transfer transistor, but may have a resettransistor adjacent to the photo-conversion device. The 5T, 6T, and 7Tpixel cells differ from the 4T pixel cell by the addition of one, two,or three transistors, respectively, such as a shutter transistor, a CMOSphotogate transistor, and an anti-blooming transistor. Further, whilethe above embodiments are described in connection with CMOS pixel cells200, 400, 500, the invention is also applicable to pixel cells in acharge coupled device (CCD) image sensor.

A typical single chip CMOS image sensor 600 is illustrated by the blockdiagram of FIG. 6. The image sensor 600 includes a pixel cell array 680having one or more pixel cells, e.g., pixel cells 200 (FIG. 2) includinglow resistance conductors 270 as described above. The pixel cells ofarray 680 are arranged in a predetermined number of columns and rows.Alternatively, the pixel array 680 could include pixel cells 400 (FIG.4) and/or 500 (FIG. 5).

In operation, the rows of pixel cells in array 680 are read out one byone. Accordingly, pixel cells in a row of array 680 are all selected forreadout at the same time by a row select line, and each pixel cell in aselected row provides a signal representative of received light to areadout line for its column. In the array 680, each column also has aselect line, and the pixel cells of each column are selectively read outin response to the column select lines.

The row lines in the array 680 are selectively activated by a row driver682 in response to row address decoder 681. The column select lines areselectively activated by a column driver 684 in response to columnaddress decoder 685. The array 680 is operated by the timing and controlcircuit 683, which controls address decoders 681, 685 for selecting theappropriate row and column lines for pixel signal readout.

The signals on the column readout lines typically include a pixel resetsignal (V_(rst)) and a pixel image signal (V_(photo)) for each pixelcell. Both signals are read into a sample and hold circuit (S/H) 686 inresponse to the column driver 684. A differential signal(V_(rst)−V_(photo)) is produced by differential amplifier (AMP) 687 foreach pixel cell, and each pixel cell's differential signal is digitizedby analog-to-digital converter (ADC) 688. The analog-to-digitalconverter 688 supplies the digitized pixel signals to an image processor689, which performs appropriate image processing before providingdigital signals defining an image output.

FIG. 7 illustrates a processor system 700 including an image sensor 600of FIG. 6. The processor system 700 is exemplary of a system havingdigital circuits that could include image sensor devices. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision, vehicle navigation, video phone, surveillancesystem, auto focus system, star tracker system, motion detection system,image stabilization system, and data compression system.

The system 700, for example a camera system, generally comprises acentral processing unit (CPU) 760, such as a microprocessor, thatcommunicates with an input/output (I/O) device 761 over a bus 763. Imagesensor 600 also communicates with the CPU 760 over bus 763. The system700 also includes random access memory (RAM) 762, and can includeremovable memory 764, such as flash memory, which also communicate withCPU 760 over the bus 763. Image sensor 600 may be combined with aprocessor, such as a CPU, digital signal processor, or microprocessor,with or without memory storage on a single integrated circuit or on adifferent chip than the processor.

It is again noted that the above description and drawings are exemplaryand illustrate preferred embodiments that achieve the objects, featuresand advantages of the present invention. It is not intended that thepresent invention be limited to the illustrated embodiments. Anymodification of the present invention which comes within the spirit andscope of the following claims should be considered part of the presentinvention.

1. A pixel cell comprising: a photo-conversion device at a surface of asubstrate; at least one contact area from which charge or a signal isoutput or received; a first insulating layer over the photo-conversiondevice and the at least one contact area; and at least one conductor incontact with the at least one contact area, the at least one conductorcomprising: a polysilicon comprising material extending through thefirst insulating layer and being in contact with the at least onecontact area.
 2. The pixel cell of claim 1, wherein a conductivematerial is over and in contact with the polysilicon comprisingmaterial, the conductive material comprising at least one of a silicideand a refractory metal.
 3. The pixel cell of claim 1, wherein the atleast one contact area is a gate electrode.
 4. The pixel cell of claim2, wherein the gate electrode is the gate electrode of one of atransfer, reset, row select, and source-follower transistor.
 5. Thepixel cell of claim 1, wherein the at least one contact area is afloating diffusion region.
 6. The pixel cell of claim 1, wherein the atleast one contact area is a source/drain region of a transistor.
 7. Thepixel cell of claim 2, wherein the conductive material comprises asilicide.
 8. The pixel cell of claim 7, wherein the conductive materialcomprises a silicide selected from the group consisting of tungstensilicide, titanium silicide, cobalt silicide, molybdenum silicide, andtantalum silicide.
 9. The pixel cell of claim 2, wherein the conductivematerial comprises a barrier metal/refractory metal layer.
 10. The pixelcell of claim 9, wherein the conductive material comprises a tungstennitride/tungsten layer.
 11. The pixel cell of claim 9, wherein theconductive material comprises a titanium nitride/tungsten layer.
 12. Thepixel cell of claim 2, wherein the conductive material comprises atungsten nitride layer.
 13. The pixel cell of claim 1, furthercomprising a second insulating layer over the photo-conversion deviceand below the first insulating layer.
 14. The pixel cell of claim 1,wherein the polysilicon comprising material has a top surface on a sameplane as a top surface of the first insulating layer.
 15. The pixel cellof claim 1, wherein a top surface of the polysilicon comprising materialis over a top surface of the first insulating layer.
 16. The pixel cellof claim 1, further comprising a plurality of contact areas and aplurality of conductors, each conductor being in contact with arespective contact area.
 17. A pixel cell comprising: a photo-conversiondevice at a surface of a substrate; a first transistor coupled to thephoto-conversion device, the first transistor having a gate electrodeand a gate insulator over the gate electrode; at least one insulatinglayer over the photo-conversion device and the first transistor; and afirst conductor in contact with the gate electrode, the conductorcomprising: a polysilicon comprising material extending through thefirst insulating layer and the gate insulator to contact the gateelectrode.
 18. The pixel cell of claim 17, wherein a conductive materialis over and in contact with the polysilicon comprising material, theconductive material comprising at least one of a silicide and arefractory metal.
 19. The pixel cell of claim 17, further comprising: afloating diffusion region coupled to the first transistor; and a secondconductor in contact with the floating diffusion region, wherein thesecond conductor comprises the polysilicon comprising material extendingthrough the at least one insulating layer and the gate insulator tocontact the gate electrode, and the conductive material over and incontact with the polysilicon comprising material.
 20. The pixel cell ofclaim 17, further comprising a second insulating layer over thephoto-conversion device and below the at least one insulating layer. 21.The pixel cell of claim 17, wherein the at least one insulating layercomprises borophosphosilicate glass.
 22. The pixel cell of claim 17,wherein the at least one insulating layer comprises tetraethylorthosilicate.
 23. An image sensor comprising: a substrate; and an arrayof pixel cells, at least one pixel cell comprising: a photo-conversiondevice at a surface of a substrate; at least one contact area from whichcharge or a signal is output or received; a first insulating layer overthe photo-conversion device and the at least one contact area; and atleast one conductor in contact with the at least one contact area, theat least one conductor comprising: a polysilicon comprising materialextending through the first insulating layer and being in contact withthe at least one contact area.
 24. The image sensor of claim 23, whereina conductive material is over and in contact with the polysiliconcomprising material, the conductive material comprising at least one ofa silicide and a refractory metal.
 25. The image sensor of claim 23,wherein the at least one contact area is a gate electrode.
 26. The imagesensor of claim 25, wherein the gate electrode is the gate electrode ofone of a transfer, reset, row select, and source-follower transistor.27. The image sensor of claim 23, wherein the at least one contact areais a floating diffusion region.
 28. The image sensor of claim 23,wherein the at least one contact area is a source/drain region of atransistor.
 29. The image sensor of claim 24, wherein the conductivematerial comprises a silicide layer.
 30. The image sensor of claim 29,wherein the conductive material comprises a silicide selected from thegroup consisting of tungsten silicide, titanium silicide, cobaltsilicide, molybdenum silicide, or tantalum silicide.
 31. The imagesensor of claim 24, wherein the conductive material comprises a barriermetal/refractory metal layer.
 32. The image sensor of claim 31, whereinthe conductive material comprises a tungsten nitride/tungsten layer. 33.The image sensor of claim 31, wherein the conductive material comprisesa titanium nitride/tungsten layer.
 34. The image sensor of claim 24,wherein the conductive material comprises a tungsten nitride layer. 35.The image sensor of claim 23, further comprising a second insulatinglayer over the photo-conversion device and below the first insulatinglayer.
 36. The image sensor of claim 23, further comprising a pluralityof contact areas and a plurality of conductors, each conductor being incontact with a respective contact area.
 37. The image sensor of claim23, further comprising at least one line coupled to the at least oneconductor, the line coupled to circuitry external to the at least onepixel cell.
 38. The image sensor of claim 23, wherein the at least onepixel cell is a four-transistor pixel cell.
 39. The image sensor ofclaim 23, wherein the at least one pixel cell is a three-transistorpixel cell.
 40. The image sensor of claim 23, wherein the at least onepixel cell is a charge coupled device-type pixel cell.
 41. A processorsystem comprising: (i) a processor; and (ii) an image sensor coupled tothe processor, the image sensor comprising: a substrate; and an array ofpixel cells, at least one of the pixel cells comprising: aphoto-conversion device at a surface of a substrate; at least onecontact area from which charge or a signal is output or received; afirst insulating layer over the photo-conversion device and the at leastone contact area; and at least one conductor in contact with the atleast one contact area, the at least one conductor comprising: apolysilicon comprising material extending through the first insulatinglayer and in contact with the at least one contact area.
 42. The systemof claim 41, wherein a conductive material is over and in contact withthe polysilicon comprising material, the conductive material comprisingat least one of a silicide and a refractory metal.
 43. The system ofclaim 41, wherein the image sensor is a CMOS image sensor.
 44. Thesystem of claim 41, wherein the image sensor is a charge coupled deviceimage sensor.
 45. A method of forming a pixel cell, the methodcomprising the acts of: forming a photo-conversion device at a surfaceof a substrate; forming a first contact area; forming at least a firstinsulating layer over the photo-conversion device and the first contactarea; forming at least one opening in the first insulating layer;providing a polysilicon comprising material within the opening and incontact with the contact area.
 46. The method of claim 45, furthercomprising the act of forming a conductive material layer over and incontact with the polysilicon comprising material, the act of forming theconductive material comprising forming at least one of a silicide and arefractory metal.
 47. The method of claim 45, wherein the act of formingthe at least one contact area comprises forming a gate electrode. 48.The method of claim 47, wherein the act of forming the at least onecontact area comprises forming a gate electrode of one of a transfer,reset, row select, and source-follower transistor.
 49. The method ofclaim 45, wherein the act of forming the at least one contact areacomprises forming a floating diffusion region.
 50. The method of claim45, wherein the act of forming the at least one contact area comprisesforming a source/drain region of a transistor.
 51. The method of claim46, wherein the act of providing the conductive material comprisesforming a silicide layer.
 52. The method of claim 51, wherein the act offorming the silicide layer comprises forming a silicide layer comprisinga silicide selected from the group consisting of a tungsten silicide,titanium silicide, cobalt silicide, molybdenum silicide, and tantalumsilicide layer.
 53. The method of claim 46, wherein the act of providingthe conductive material comprises forming a barrier metal/refractorymetal layer.
 54. The method of claim 53, wherein the act of providingthe conductive material comprises forming a tungsten nitride/tungstenlayer.
 55. The method of claim 53, wherein the act of providing theconductive material comprises forming a titanium nitride/tungsten layer.56. The method of claim 45, further comprising the act of forming asecond insulating layer over the photo-conversion device and below thefirst insulating layer.
 57. The method of claim 45, further comprisingthe act of planarizing the polysilicon comprising material and the firstinsulating layer such that the polysilicon comprising material has a topsurface on a same plane as a top surface of the first insulating layer.58. The method of claim 57, further comprising the act of forming aconductive material layer over and in contact with the polysiliconcomprising material, wherein the act of forming the conductive materialcomprises forming a polysilicon/barrier metal/refractory metal layer.59. The method of claim 57, further comprising the act of forming aconductive material layer over and in contact with the polysiliconcomprising material, wherein the act of forming the conductive materialcomprises forming a polysilicon/silicide layer.
 60. The method of claim45, further comprising the acts of forming a plurality of contact areasand forming a plurality of openings, each opening formed to expose arespective contact area, wherein the polysilicon comprising layer isformed within each of the openings and in contact with a respectivecontact area.
 61. The method of claim 45, further comprising the actsof: forming at least one line coupled to the at least one conductor; andcoupling the at least one line to circuitry external to the at least onepixel cell.
 62. A method of forming a pixel cell, the method comprisingthe acts of: forming a photo-conversion device at a surface of asubstrate; forming a first transistor coupled to the photo-conversiondevice, the first transistor having a gate electrode and a gateinsulator over the gate electrode; forming at least one insulating layerover the photo-conversion device and the first transistor; forming afirst opening in the at least one insulating layer and the gateinsulating layer, the first opening extending to the gate electrode;providing a polysilicon comprising layer in the first opening and incontact with the gate electrode.
 63. The method of claim 62, furthercomprising the acts of: providing a conductive layer over and in contactwith the polysilicon comprising layer, the conductive layer comprisingat least one of a silicide and a refractory metal.
 64. The method ofclaim 62, further comprising the acts of: forming a floating diffusionlayer coupled to the first transistor; and forming a second opening inthe second insulating layer, the second opening extending to thefloating diffusion region, wherein the act of providing the polysiliconcomprising layer comprises providing the polysilicon comprising layer inthe second opening.
 65. The method of claim 62, further comprising theact of forming first and second insulating layers over thephoto-conversion device.
 66. The method of claim 62, wherein the act offorming the at least one insulating layer comprises forming aborophosphosilicate glass layer.
 67. The method of claim 62, the act offorming the at least one insulating layer comprises forming tetraethylorthosilicate layer.